1. Related Applications
This application is related to: U.S. patent application Ser. No. 07/461,165, entitled "High Speed Active Bus", filed on Jan. 5, 1990, now abandonded; U.S. patent application Ser. No. 07/886,045, entitled "Multiple Bus Architecture", filed May 19, 1992, now U.S. Pat. No. 5,263,139 U.S. patent application Ser. No. 07/886,671, entitled "A Bus Architecture for Integrated Data and Video Memory", filed May 19, 1992, now U.S. Pat. No. 5,265,218; and U.S. patent application Ser. No. 07/886,413, entitled "Single In-Line Memory Module", filed May 19, 1992, now U.S. Pat. No. 5,270,964.
2. Field of the Invention
The present invention relates to the field of computer systems and associated memory structures. More particularly, the present invention relates to method and apparatus for memory control, specifically for controlling dynamic and video random access memory (RAM) modules.
3. Art Background
A typical computer system is comprised of a processor or CPU, a memory subsystem, an input/output subsystem, and other specialized subsystems. Communication between the processor and the subsystems is usually accomplished through one or more communication pathways known as buses. In many computer systems, the processor and subsystems are coupled for communication over a common bus.
As computer technology progresses, the performance of the processor and other subsystems improves. The improved performance in one subsystem creates the need for improved performance in the other subsystems. For example, as the performance of the processor improves, the memory or input/output subsystem is often redesigned to accommodate the improved processor performance. Similarly, as the performance of the memory subsystem improves, the processor architecture is changed to take advantage of the improved memory subsystem performance.
With the progressive performance improvements in processor, memory subsystem, and specialized subsystems, the communication pathways of the computer system often become performance "bottlenecks." In past computer systems, the communication pathway architecture was designed in response to improvements to the processor and subsystems. The performance of such systems was not easily improved without redesigning the entire system including the communication pathways.
A multiple bus architecture provides flexible communication between processors, memory subsystems, and specialized subsystems over multiple high performance communication pathways. The high performance communication pathways enable communication for multiple processors and multiple subsystems, and enables flexible upgrade to higher performance processors and subsystems.